The present invention generally relates to finite impulse response (FIR) circuits and disk units, and more particularly to an asymmetric FIR circuit which corrects and eliminates a group delay distortion and to a disk unit which uses such a FIR circuit.
FIG. 1 shows an important part of an example of a hard disk drive (HDD). An external write signal (or data) is recorded on a recording medium 114 such as a magnetic disk via a hard disk controller (HDC) 111, a write circuit 109, a write amplifier 103 of an amplifier part 101 which is indicated by a dotted line, and a magnetic head 115. The recorded signal (or data) on the recording medium 114 is read by the magnetic head 115 and is output to an external unit (not shown) via a read amplifier 102 of the amplifier part 101, an automatic gain control (AGC) circuit 103, a filter 105, a FIR circuit 107, a demodulator 108 and the HDC 111. When carrying out digital signal processing in the FIR circuit 107, the demodulator 108, the HDC 111 and the like, an analog-to-digital converter is provided between the filter 105 and the FIR circuit 107 to convert analog signals into digital signals.
The FIR circuit 107 is a kind of shaping circuit for shaping the signal waveform which is distorted during processes such as writing and reading of the signals and the processes carried out by the AGC circuit 104 and the filter 105. A microprocessor unit (MPU) 112 makes a reference to a memory 113 and sets parameters to the FIR circuit 107.
The read amplifier 102 amplifies a weak signal read by a read head R of the magnetic head 115, and supplies the amplified read signal to a read channel 110 which is indicated by a dotted line.
On the other hand, the write amplifier 103 amplifies the write signal and drives a write head W of the magnetic head 115 depending on the write signal. The write circuit 109 carries out a signal processing with respect to the write signal from the HDC 111 before supplying the write signal to the write amplifier 103.
The AGC circuit 105 is provided to maintain the amplitude of the read signal constant. The filter 105 is provided for noise elimination. Instead of providing the FIR circuit 107 for waveform shaping, it is possible to provide a high-frequency boost circuit. The demodulator 108 converts the read signal into the data "0" and "1".
The HDC 111 connects the HDD to the external unit. The MPU 112 controls the general operation of the HDD, including the setting of the parameters of the FIR circuit 107. The memory 113 stores a firmware of the HDC 111 and various parameter values.
FIG. 2 shows a conventional FIR circuit 7 which may be used as the FIR circuit 107. For the sake of convenience, it is assumed that coefficients are automatically set, that is, the coefficients are determined to optimum or approximately optimum values depending on signal changes.
A read signal Vin applied to an input terminal 20 is supplied to the FIR circuit 7 via an AGC circuit 1 and a filter 2, and an output signal Vout having a shaped waveform is output from the FIR circuit 7 and obtained via an output terminal 21.
The FIR circuit 7 includes a delay line 15, adders 5 and 9, and a multiplier 6 which are connected as shown. The delay line 15 includes an even number of delay circuits 3 and 4 and an odd number of equi-distant taps. Each of the delay circuits 3 and 4 has a delay time T which is approximately equal to a signal time interval. FIG. 2 shows a case where 2 delay circuits 3 and 4, and 3 taps are provided.
A coefficient determination circuit 8 supplies a signal S to one input terminal of the multiplier 6 based on an output signal VN of the adder and the output signal Vout of the FIR circuit 7, so that the output signal Vout of the FIR circuit 7 converges to "0", "1" or "-1".
In this particular case, taps A, B and C are provided in the delay line 15, and the tap B is regarded as a center tap. The number or the order of the taps A through C is determined by regarding the center tap B as a reference. Hence, the center tap B is regarded as a 0th tap, the tap A on the left of the center tap B is regarded as a -1st tap, and the tap C on the right of the center tap B is regarded as a +1st tap.
As described above, the FIR circuit 7 receives the read signal Vin from the input terminal via the AGC circuit 1 and the filter 2. In the FIR circuit 7, the adder 5 adds an output signal V.sub.A of the -1st tap A and an output signal V.sub.C of the +1st tap C. The output signal VN of this adder 5 and the output signal S of the coefficient determination circuit 8 are multiplied in the multiplier 6. The adder 9 adds an output signal V.sub.B of the center (0th) tap B and an output signal VNC of the multiplier 6. As a result, the adder 9 outputs the output signal Vout having the shaped waveform.
Next, a general description will be given of the waveform distortion. FIGS. 3A through 3D are diagrams for explaining the waveform distortion with respect to a single pulse signal.
As shown in FIG. 3A, a normal waveform which is not distorted has a regular level "1" at a signal point T0 and a level "0" at other sampling points.
But in the case of distorted symmetrical waveforms which are symmetrical to the right and left, the waveforms are distorted symmetrically to the right and left about the signal point T0 and the level is not "0" at the sampling points other than the signal point T0, as shown in FIGS. 3B and 3C. FIG. 3B shows the distorted symmetrical waveform which is distorted symmetrically to the right and left, having a level smaller than "1" at the signal point T0. FIG. 3C shows the distorted symmetrical waveform which is distorted symmetrically to the right and left, having a level larger than "1" at the signal point T0 and a level larger than "0" at the sampling points other than the signal point T0. In other words, the signal amplitude is generally smaller than the regular levels in the case of the distorted symmetrical waveform shown in FIG. 3B, and the signal amplitude is generally larger than the regular levels in the case of the distorted symmetrical waveform shown in FIG. 3C.
Further, FIG. 3D shows a distorted asymmetrical waveform which is distorted asymmetrically. When viewed from the signal point T0, the distortion of the distorted asymmetrical waveform shown in FIG. 3D is asymmetrical to the right and left.
Of course, in actual circuits, the distortion is not generated in the single pulse signal as shown in FIGS. 3B through 3D, but is generated due to the mutual effects of pulse signals.
According to the conventional FIR circuit 7, no problem occurs if the read signal Vin has a waveform which is symmetrical to the right and left and includes no distortion as shown in FIG. 4A. In this case, the waveform has the regular levels "0", "1" and "-1" at the sampling points as shown in FIG. 4B.
However, the waveform of the read signal Vin may be distorted as shown in FIG. 5A if the group delay characteristic is not flat for the filter 2, the AGC 1 and the like. In other words, the waveform of the read signal Vin may be distorted asymmetrically to the right and left, as indicated by portions PA and PB in FIG. 5A.
If the read signal Vin is distorted as shown in FIG. 5A, the output signal Vout of the FIR circuit 7 becomes as shown in FIG. 5B, and the asymmetrical distortion cannot be corrected. More particularly, the signal amplitude deviates from the regular level "0", and an erroneous detection of the level "0" is likely to occur.
Particularly due to the increased processing speeds of the recent disk units, it is becoming more and more difficult to design the amplifiers and the filters to satisfy the specifications, and there is a tendency for the group delay distortion to increase. However, the conventional FIR circuit 7 cannot cope with the asymmetrical distortions, and there was a problem in that a read error is easily generated when the conventional FIR circuit 7 is used in disk units.